Contact:
Bob Fess
ALDEC, Inc.
Tel.(702) 990-4400 ext. 227
bobf@aldec.com

     Henderson Nevada, March 13th, 2001 -- The HES™ (Hardware Embedded Simulation™) simulation accelerator technology developed by Aldec, Inc. is being tested and evaluated by Agilent Technologies in Loveland, Colorado. HES significantly reduces design times and time-to-market performance of some of Agilent's most advanced manufacturing test equipment products.

Using HES for Agilent Test Devices
The prototyping system will be used by Agilent's design team for the development of hardware and several million lines of code for a product used to test their customers' products. As the project continues, Agilent and Aldec engineers will optimize the HES hardware and Active-HDL™ software provided by Aldec to achieve significant reductions in design time.

Aldec's HES module is installed on an HP Kayak computer's PCI bus. The engineers then use Aldec's Incremental Prototyping™ methodology supported by the HES module and the Design Verification Manager to implement Agilent's initial version of the test equipment. HES supports incremental insertion of synthesized blocks of logic into the FPGA and allows Agilent engineers to maintain integrity of design while it is resident in both the FPGA and Active-HDL simulator as the design evolves.

Agilent's test application software will then be integrated and optimized in a hardware/software co-verification process supported by HES. Incremental Prototyping permits efficient hardware/software optimization throughout the development process. Iterative adjustments in both hardware and software components can be reverified in microseconds, avoiding costly software simulation iteration and supporting Agilent's time-to-market goals.

About HES™ Hardware Accelerator
Aldec's Incremental Prototyping technology, used in conjunction with HES, allows the user to divide large designs into smaller logical blocks of gates and to then implement each block incrementally to an FPGA device located on the HES board. Stored blocks of the design can then be simulated instantaneously with those still residing in software simulators, significantly reducing time required for simulation runs.

About Aldec
Aldec has offered PC-based design entry and simulation solutions to FPGA designers for more than 16 years. Aldec, Inc., headquartered in Henderson, Nevada, produces a universal suite of Windows-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the Windows-based EDA market as the fastest growing privately held EDA supplier in the world.

In March 2001, Aldec announced creation of its HES Business Unit. The HES unit has responsibility for the development and marketing of hardware acceleration products compatible with EDA simulation products from many vendors supporting an industry standard PLI interface.

Additional information about Aldec, Active-HDL, and HES™ is available at http://www.aldec.com

Active-HDL, Hardware Embedded Simulation, and Incremental Prototyping are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners